High-Level Synthesis, Also known as Electronic System Level Synthesis and C Synthesis, High-Level Synthesis is an automated design procedure, that converts the algorithmic description of a system into the corresponding hardware circuit. In this process, which is actually a part of the high-level design flow, the system behaviour is described at a very high level of abstraction. This method improves productivity and reduces the chance of error. 
Brief History: 
Synopsys introduced Behavioral Compiler, the first generation behavioural synthesis tool, in 1994. Verilog was used as the input language. 10 years later, various next-generation High-Level Synthesis(HLS) tools were introduced in the market. These tools offered circuit synthesis, described in a high-level language and Register Transfer Level. Manufacturers of these tools provided extensive PC support for a wide range of tool issues. 
How It Is Done?: 
The first step in HLS is to implement the system algorithm in a high-level language, such as ANSI C, C++, System C, etc. After that, the synthesis tool generates the technical details, which is required for hardware implementation. Most of the HLS design methods use conventional logic synthesis tools by generating a Register Level Transfer (RTL) logic implementation from the system algorithm. The RTL logic is used by the traditional logic synthesis tools to generate a gate-level design. The HLS tools convert the partially timed functional code into a fully timed RTL design. The basic objective of HLS is to enable the designers to develop and test the hardware efficiently. It also gives the designers better control over the design architecture optimization. 

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