This document describes the development of a Large Language Model (LLM) specifically tailored for explaining VHDL code within a high-performance processor design environment. Recognizing the unique requirements of such settings, including data security and leveraging existing design knowledge, the researchers employed extended pretraining (EPT) and instruction tuning on a base LLM using proprietary data. They created specialized test sets and utilized an LLM-as-a-judge approach to efficiently evaluate model performance, finding significant improvements in explanation accuracy compared to the original model. The work highlights the potential of customized LLMs to enhance productivity and facilitate knowledge transfer in complex hardware design workflows.

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