Hardware-Conscious Data Processing (ST 2025) - tele-TASK

Por: Prof. Dr. Tilmann Rabl
Hardware development continuously advances, with different technologies improving at different paces. While the number of transistors in a CPU package grows, the single-core performance stagnates due to physical limitations. These trends require changes in data processing to keep database management systems efficient. In this lecture, we will take a look at current computer architectures and accelerator technologies and how they can be used for efficient data processing. We will cover CPU and memory architecture, the storage hierarchy, modern memory and storage technologies, such as NVMe, fast interconnects, such as Infiniband, NVLink, and CXL, and accelerators, such as GPUs and FPGAs. The course has a significant practical part, where the students learn to implement data structures and algorithms tailored to hardware-conscious data processing.
26 episodios disponibles

Latest episodes of the podcast Hardware-Conscious Data Processing (ST 2025) - tele-TASK

Task 4: GPU Join 15/07/2025
Summary 09/07/2025
Field Programmable Gate Arrays 08/07/2025
Data Processing on GPUs II 02/07/2025
Data Processing on GPUs 01/07/2025
Networking 25/06/2025
Networking 24/06/2025
Storage 18/06/2025
Task 3: Buffer Manager 17/06/2025
Compute Express Link 11/06/2025
Processing in Memory 10/06/2025
Concurrency and Synchronization & Non-uniform Memory Access 04/06/2025
Multicore Parallelism & Concurrency and Synchronization 03/06/2025
Multicore Parallelism 21/05/2025
Data Structures 20/05/2025
Profiling 13/05/2025
Vectorized Execution 07/05/2025
Task 1: Query Processing 06/05/2025
Query Execution Models 30/04/2025
Prefetching 29/04/2025
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