Condor Currents

Por: Condor Computing

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Latest episodes of the podcast Condor Currents

SPICE: Speculative Prefetching with Low-Rank Expert Surrogates and Heterogeneous Orchestration for MoE Inference Acceleration

Formal Performance and Compile Time Guarantees for Compiler Optimization Heuristics

From Retrieved Context to Runtime Control: Adaptive Compression for Edge-based RAG

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

FPGA Lifecycle Management for RISC-V Systems

ETHEREAL: A 25.6-$μ$s/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge

Testing the EPYC Conjecture on Real Hardware: MoA-Guided Dense Matrix Multiplication on NCSA Delta (AMD EPYC 7763 Milan)

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

What Actually Serializes GPU LZ77 Decode: Three Decoders, Three Mechanisms, and an Encode-Time Lever That Removes the Last One

SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon

Why Do Prefetchers Fail? Let Agents Answer

APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference

ArchAgent v2: A Case Study with the Data Prefetching Championship

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

Heterogeneous LLM Serving with General-Purpose Processing-Near-Memory for Retrieval-Based Sparse Attention

PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving

Architectural Implications of Agentic AI Workflows

LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension

Themis: Software-Defined Hardware Prefetching

Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systems

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